Nowadays, many integrated circuits (ICs) are designed to perform a wide variety of computational tasks. To this end, such an IC may comprise a plurality of different circuit portions, e.g. cores, each designed to perform one of said computational tasks. An example of such a multi-tasking IC design is the system-on-chip concept. Usually, such ICs perform only a subset of the computational tasks at the same time, which means that the other circuit portions do not perform any tasks. To avoid unnecessary power consumption by such idle circuit portions, these circuit portions are temporarily disconnected from the power supply until their functionality is required again.
There are several IC design principles available to facilitate disconnecting a circuit portion from its power supply. FIG. 1 shows such a principle. A core 100 has internal power lines 130 and 140, i.e. a virtual ground and a virtual supply line. The virtual supply 130 is connected to a supply line 110 via a pMOS power switch 115 for gating the power supply line 110, e.g. VDD, and the virtual ground line 140 is connected to a ground line 120 via an nMOS power switch 135 for gating the ground line 120, e.g. VSS. An inverter chain 150 comprises a first inverter 152 for controlling the nMOS power switch 135 and a second inverter 154 for controlling the pMOS power switch 115.
As shown in FIG. 2, which shows a possible layout of a power switch block 200, the power switch block typically comprises a number of segments 220, with each segment comprising a pair of power switches 115, 135 and a pair of drivers for the power switches, e.g. inverters 152 and 154. The number of segments is typically governed by performance requirements such as the maximum allowable resistance of the power switches in the power switch block 200.
Currently, the power switch block 200 is designed based on the aforementioned performance requirements using standard library segment components, such as the use of a standard transistor as a power switch. Such a standard transistor usually has a ratio of its gate width and gate length (hereafter referred to as the width/length ratio) that is relatively small, which means that such a transistor has a relatively high resistance. Thus, in order to meet the performance requirements of a power switch, which may include a maximum allowable resistance, a maximum allowable latency to reach a full power-up or power-down and so on, the power switch block 200 typically must contain a large number of segments 220 to comply with such performance requirements. This not only adds area overhead but also complexity to the IC design because a substantial number of interconnections has to be provided for. In addition, the use of standard transistors may make it difficult to accurately meet the performance requirements.